1. Executive Summary & Industry Architecture

The semiconductor industry is the most consolidated, capital-intensive, and geographically concentrated industrial complex on the planet. Producing a single advanced chip requires the coordinated output of roughly 16,000 specialized inputs sourced from more than 30 countries, passing through hundreds of process steps in facilities that cost USD 15–25 billion to build. Despite massive global revenue (projected at USD 760 billion in 2026 by WSTS), the entire stack rests on a handful of monopolies and near-monopolies.

The industry has six structural layers, each with its own oligopoly, technology curve, cost share, and geographic footprint:

• Layer 1 — Design Tools (EDA): Synopsys, Cadence, Siemens EDA control ~78–85% of global EDA revenue. EDA + IP together represent roughly 8–12% of the bill of materials of an advanced SoC.
• Layer 2 — Semiconductor IP: Arm dominates licensable processor IP (~40% share); Synopsys and Cadence dominate interface, memory, and foundation IP. RISC-V is rapidly disrupting this layer.
• Layer 3 — Materials: Shin-Etsu and SUMCO control ~53% of silicon wafers. JSR, TOK, Shin-Etsu, and Fujifilm together control ~87–91% of global photoresist. Photomasks are dominated by Photronics, Toppan, DNP.
• Layer 4 — Equipment (WFE): Five firms — Applied Materials, ASML, Lam Research, Tokyo Electron, KLA — control 60–70% of wafer fab equipment revenue. ASML is the sole global supplier of EUV and High-NA EUV lithography.
• Layer 5 — Manufacturing (Fabs): TSMC controls roughly 70% of the foundry market and over 90% of leading-edge (≤7nm) capacity. Intel and Samsung are the only other firms attempting sub-3nm production.
• Layer 6 — Packaging & Test (OSAT): ASE, Amkor, JCET lead conventional and advanced packaging. TSMC dominates CoWoS (the dominant 2.5D AI packaging platform) with >95% utilization and a 2-year backlog.

1.1 The Three Geographic Choke Points

Three places on Earth can shut down the global semiconductor industry within weeks if disrupted:

• Hsinchu, Taiwan — TSMC's leading-edge fabs produce ~90% of all chips below 7nm. There is no near-term substitute.
• Veldhoven, Netherlands — ASML's only EUV/High-NA EUV factory. No EUV scanner has ever been built outside this facility.
• Yokkaichi & Shin-Etsu sites, Japan — Roughly half of all silicon wafers and photoresists used in the world's fabs originate from a small cluster in Japan.

2. Transistor Architectures: Planar → FinFET → GAA → CFET

Every node generation has been enabled by either lithography improvements or by a transistor architecture change. The progression below is the spine of the modern semiconductor roadmap.

2.1 Planar MOSFET (Pre-2011, ≥22nm logic, ≥45nm at most foundries)

Planar bulk-CMOS transistors place the gate on top of a flat silicon channel; the gate controls current only from one side. As gate length shrank below ~28nm, short-channel effects (drain-induced barrier lowering, sub-threshold leakage, punch-through) made planar geometry uneconomic for high-performance digital logic. Planar is still the dominant architecture for analog, RF, power management ICs, image sensors, MEMS, BCD power technology, and most automotive microcontrollers built at ≥40nm.

2.2 FinFET (2011–2024, 22nm down to 3nm)

Intel introduced FinFET (Tri-Gate) in volume at the 22nm node in 2011; TSMC followed at 16nm in 2014; Samsung and GlobalFoundries at 14nm. The fin is a vertical silicon ridge wrapped on three sides by the gate, dramatically reducing leakage and improving switching speed. FinFETs scaled across N16, N10, N7, N5, N4, and TSMC extended FinFET all the way to N3 (3nm) — a remarkable 12-year run that defined the smartphone, datacenter, GPU, and high-end auto chip era.

2.3 Gate-All-Around / Nanosheet (2022 onward, 3nm/2nm and beyond)

Below 3nm the fin width must shrink to ~5nm to retain electrostatic control, and at that point the fin is so thin that quantum effects and process variation degrade yield. The industry's response is to rotate the fin and slice it into stacked horizontal sheets — the gate now wraps around all four sides of each channel sheet. This is called Gate-All-Around (GAA), nanosheet, or by vendor-specific names:

• Samsung MBCFET (Multi-Bridge Channel FET) — first to ship in 2022 at 3nm; struggling with yield.
• TSMC N2 (nanosheet) — began limited shipping in Q4 2025; high-volume ramp through 2026.
• Intel RibbonFET — introduced at Intel 18A with backside power delivery (PowerVia); shipping in early 2026.

GAA improves drive current (more channel surface area per footprint) and allows independent tuning of channel width per sheet, which is impossible with FinFETs whose width is quantized by fin count.

2.4 Forksheet, CFET and Beyond (2027–2032)

Imec's roadmap places forksheet at A10/A7, then Complementary FET (CFET) — vertically stacking NMOS over PMOS in a single transistor footprint — around the A7 node circa 2031. Peking University and others have proposed FlipFET as an alternative architecture. In parallel, 2D channel materials (MoS₂, WSe₂) and directed self-assembly nanopatterning are being investigated as channel and patterning options for sub-A7 generations.

Architecture Transition Summary

3. Process Nodes & Application Suitability

Process node names — 250nm, 90nm, 28nm, 7nm, 3nm — historically referred to the physical gate length. Since roughly 2011, node names have become marketing labels: TSMC's "5nm," Samsung's "5nm," and Intel's "7" are not directly comparable in transistor density or contacted poly pitch. The naming convention now reflects generational performance/density gains rather than any single physical dimension.

3.1 Node Categories

• Mature/Legacy nodes (≥90nm to 1µm): Power management, automotive MCUs, RF, MEMS, sensors, radiation-hardened space/defense parts, BCD power, smart-card chips. Often the only choice when reliability, radiation tolerance, or cost (USD 1–5 per chip) matters more than performance.
• Trailing-edge nodes (90nm, 65nm, 55nm, 40nm): Microcontrollers, display drivers, image sensors, IoT SoCs, PMICs, automotive infotainment.
• Mainstream nodes (28nm, 22nm, 16/14nm): The "sweet spot." 28nm is the most economically efficient node ever produced. 16/14nm dominates volume automotive ADAS, mid-tier smartphones, and networking.
• Advanced nodes (10nm, 7nm, 5/4nm): Premium smartphone APs, GPUs, server CPUs, AI accelerators. EUV becomes mandatory at 7nm and below.
• Leading-edge nodes (3nm, 2nm, A14, A10): Apple A/M-series, NVIDIA datacenter GPUs, AMD MI accelerators, hyperscaler custom silicon. Mask costs USD 15–30M per design; NRE USD 400–800M+ per tape-out.

3.2 Node-to-Application Suitability Matrix

3.3 Application Deep Dive: Why "Older" Nodes Aren't Inferior

Space & Satellite Electronics — typically 250nm, 180nm, 130nm, 90nm

Smaller transistors are MORE susceptible to single-event upsets (SEU), single-event latch-up (SEL), and total ionizing dose (TID) damage from cosmic rays. Radiation-hardened designs use larger nodes where each transistor stores more charge and the design margins absorb radiation events. Major rad-hard suppliers: BAE Systems, Honeywell, Cobham/Caes, Microsemi/Microchip, STMicro, TI HiRel, Frontgrade Technologies.

Automotive — primarily 90nm to 16nm; ADAS climbing toward 5nm

Automotive parts require 15-year availability, AEC-Q100 grade-0 (-40°C to +150°C), zero-defect quality (DPPM <1). Powertrain MCUs use 90nm–40nm. ADAS drives adoption of 28nm (FDSOI for radar), 16/14nm, and 7nm/5nm for autonomous driving compute (NVIDIA Drive Thor, Mobileye EyeQ6). SiC and GaN serve EV inverters and onboard chargers.

Defense & Avionics — 250nm to 28nm depending on subsystem

Legacy F-16 avionics use ~90nm; F/A-18 and F-22 mission computers use ~65nm; newer F-35 software upgrade modules use 45nm; secure tactical communications use 45nm. Radiation-hardened capabilities are typically manufactured on 130nm or even 250nm. The DoD's RAMP-C program is shifting parts toward 14nm and 7nm domestic production.

AI/HPC — 5nm, 4nm, 3nm, moving to 2nm

AI accelerators (NVIDIA H100/B200, AMD MI300X/MI400, Google TPU v5/v6, AWS Trainium 2/3) live at the absolute leading edge because performance-per-watt directly determines training cost at hyperscale. These chips also drive the 2.5D advanced packaging market via TSMC CoWoS.

4. Lithography Ecosystem

Lithography is the most expensive and the most monopolized segment of semiconductor manufacturing. The lithography stack alone accounts for roughly one-third of total wafer processing cost at advanced nodes.

4.1 Lithography Technology Generations

4.2 Players & Market Concentration

ASML (Veldhoven, Netherlands) — Absolute Monopoly at the Leading Edge

ASML is the sole global supplier of EUV (NXE platform) and High-NA EUV (EXE platform) scanners. As of 2024–2025, ASML holds 100% market share in EUV and approximately 85–95% of total lithography equipment by revenue. Annual EUV output is capped near 50 systems globally. EUV scanners list at USD 200–250 million; High-NA EUV at ~USD 380 million each. ASML's order backlog exceeded EUR 38.8 billion.

Nikon (Japan)

Nikon attempted EUV development and exited. Competes only in ArF dry and ArF immersion at mature nodes. ~2.5–3% share by shipment value in 2024.

Canon (Japan)

Exited EUV; betting on Nanoimprint Lithography (NIL). NIL claims 5nm-equivalent resolution at lower cost. Adoption nascent. Canon holds ~33% shipment-volume share in i-line.

SMEE (Shanghai Micro Electronics Equipment, China)

China's domestic lithography champion. Currently capable at ~90nm with claimed 28nm in development. Cannot supply EUV.

4.3 The EUV Subsystem Supply Chain

• Light source — Cymer (acquired by ASML 2013); LPP with 50,000 tin droplets/sec vaporized by CO₂ laser.
• CO₂ drive laser — Trumpf (Germany). Sole source.
• Optics — Carl Zeiss SMT (Germany). All reflective EUV mirrors. Sole source. Molybdenum-silicon multilayer coatings.
• Pellicles — Mitsui Chemicals (Japan), ASML, others. Must survive 13.5nm heat.
• Mask blanks — Hoya, AGC (Japan). Ultra-low defect density synthetic quartz.
• Patterned masks — Photronics (US), Toppan (Japan), DNP (Japan). EUV masks cost USD 250,000–400,000 each; full set USD 15–30M.

5. Wafer Fabrication Equipment (WFE)

The "big five" WFE suppliers — Applied Materials, ASML, Lam Research, Tokyo Electron, KLA — collectively control 60–70% of WFE revenue.

5.1 Applied Materials (Santa Clara, US) — ~17–20% WFE share

Broadest WFE vendor: epitaxial deposition, PVD, CVD, ALD, ion implantation, RTP, CMP, metrology. Key customers: TSMC, Intel, Samsung, Micron, SK hynix.

5.2 Lam Research (Fremont, US) — ~11–15% WFE share

Etch & deposition specialist. Dominates dielectric/conductor etch for FinFET/GAA structures. Leader in 3D NAND deposition. Critical for high-aspect-ratio etching (3D NAND now >300 layers). Vantex/Sense.i platforms.

5.3 Tokyo Electron (Tokyo, Japan) — ~9–12% WFE share

Near-monopoly (~88% with Screen) on coater/developer track tools. Strong in plasma etch, thermal, cleaning, wafer probers.

5.4 KLA Corporation (Milpitas, US) — ~7–8% WFE share

Holds >50% of metrology and inspection market. Detects defects, measures critical dimensions, overlay, film thickness. Provides the data feedback that lets a fab achieve >90% yield. No peer competitor.

5.5 Other Significant WFE Players

• Screen Holdings (Japan): Wafer cleaning, coater/developers (with TEL ~88% global share)
• ASM International (Netherlands): ALD leader — Pulsar, Eagle, Synergis — critical for GAA work-function metals
• Hitachi High-Tech (Japan): CD-SEM, e-beam metrology, etch, FIB
• Advantest & Teradyne: Back-end ATE for logic, memory, SoC test
• ASMPT, Besi, Kulicke & Soffa: Advanced packaging bonders (hybrid bonding: Besi)
• Chinese WFE (AMEC, Naura, ACM Research, Piotech, Hwatsing): Focused on 28nm and above; rapidly improving

5.6 WFE Equipment Spend by Process Step

6. Semiconductor Materials

The 2025 global semiconductor materials market is roughly USD 72 billion. Japan dominates virtually every materials segment.

6.1 Silicon Wafers — The Substrate

Top 5 suppliers hold ~80% of 300mm wafer volume. Shin-Etsu and SUMCO together hold ~53%.

6.2 Photoresist & Ancillary Lithography Chemicals

6.3 Photomasks (Reticles)

Leading fabs operate captive mask shops (TSMC, Intel, Samsung). Merchant suppliers: Photronics (US, largest), Toppan (Japan), DNP (Japan). Hoya and AGC (Japan) supply EUV mask blanks — a near-duopoly.

6.4 CMP Slurries & Pads

• CMP Slurries: Entegris/CMC Materials (global leader); Resonac, Fujimi, Versum/Merck, Soulbrain, KCTech.
• CMP Pads: DuPont (dominant — IC1000); Fujibo, Thomas West, JSR Micro.

6.5 Process Chemicals & Sputtering Targets

Hundreds of UPW chemicals at parts-per-trillion purity: Stella Chemifa, Morita, Kanto Chemical, Mitsubishi Chemical, BASF, Honeywell, Solvay, Avantor. Sputtering targets (PVD): JX Nippon Mining, Tosoh, Materion, Honeywell, Plansee, Heraeus. ALD/CVD precursors: Versum/Merck, Air Products, Adeka, Resonac, SK Specialty.

7. Industrial & Specialty Gases

A modern fab consumes 50–60+ different gases. The 2025 specialty gas market for electronics is approximately USD 2.7–3 billion; total electronics-relevant gas market exceeds USD 8 billion.

7.1 Bulk Gases — The "Big Five" Industrial Gas Players

These five hold ~55–70% of the high-purity gas market. They typically build dedicated air separation units (ASUs) on-site at each fab.

7.2 Critical Specialty Gases & Their Roles

7.3 Geographic Choke Points in Gases

• Neon: Until 2022, Ukraine produced ~40–50% of high-purity neon. The Russian invasion forced rapid shift to Chinese, US, and Korean sources. Lithography excimer lasers cannot operate without neon.
• Helium: US Federal Reserve, Qatar, Algeria, Russia, Tanzania are the only major sources.
• C₄F₆: Kanto Denka (Japan) is effectively a sole supplier for key variants critical to 3D NAND etch.

8. Electronic Design Automation (EDA) Tools

EDA software turns a chip designer's RTL description into a manufacturable layout. The 2024 market was approximately USD 16–18 billion. Three companies hold ~78–85% of revenue.

8.1 The Big Three (and Now Four)

With Synopsys' 2025 Ansys acquisition, "Big 3" becomes effectively "Big 2 + 1" holding ~85–90% of global EDA revenue.

8.2 EDA Tool Flow

• Front-end: RTL simulation (VCS, Xcelium, Questa), formal (JasperGold, VC Formal), HLS (Catapult, Stratus)
• Synthesis: Design Compiler / Fusion Compiler, Genus
• Place & route: Innovus, IC Compiler II / Fusion Compiler
• Static timing: PrimeTime, Tempus
• Power signoff: Redhawk-SC, Voltus
• Physical verification (DRC/LVS): Siemens Calibre (de-facto standard), Pegasus, IC Validator
• Parasitic extraction: Calibre xACT, Quantus, StarRC
• Custom/analog: Cadence Virtuoso (industry standard), Synopsys Custom Compiler
• Emulation: Palladium Z2, ZeBu, Veloce

8.3 EDA Cost as % of Chip Cost

• Leading-edge AI accelerator (3nm/5nm) in volume: EDA + IP = ~7–12% of total chip cost
• Mid-volume designs (16nm auto ASIC): EDA + IP = ~15–25%
• Low-volume specialty: EDA + IP can exceed 30%
• Industry-wide: EDA revenue (~USD 18B) ≈ 3% of semiconductor revenue (~USD 630B in 2024)

9. Semiconductor IP & Processor Architectures

Modern SoCs are 70–95% licensed IP — only the differentiating "secret sauce" is custom-designed. The 2024 IP market reached USD 8.49 billion, growing >20% YoY. Top four IP vendors hold ~75–84% of revenue.

9.1 Top IP Vendors

9.2 ARM vs RISC-V

ARM is closed-source, license/royalty-based; RISC-V is open standard, royalty-free. Since 2020, RISC-V has rapidly gained ground in MCUs, AI accelerators, and Chinese designs (accelerated by US export controls). Major adopters: Western Digital, Alibaba T-Head (XuanTie), Tenstorrent, NVIDIA (control cores), SiFive, Andes. RISC-V design starts grew ~22% YoY in 2024.

9.3 IP Royalty Economics

Per-unit royalties: 1–3% of chip selling price for processor IP, plus upfront fees of USD 1–10M per core. Total IP royalty burden on a fully-loaded SoC can exceed 50% of design NRE costs. ARM's per-unit model means a USD 1,000 smartphone AP may pay ARM USD 8–15.

10. Foundries, IDMs & Manufacturing

10.1 Foundry Market Share (Q3 2025)

10.2 Memory IDMs

11. Advanced Packaging

Advanced packaging has become the second pillar of Moore's Law. The 2025 market reached ~USD 43.8 billion, growing 10–11%/year, with 2.5D/3D the fastest-growing platform.

11.1 Foundry Advanced Packaging Platforms

11.2 OSAT Players

• ASE Technology (Taiwan): Largest OSAT; SiP leader; SPIL subsidiary; ~25% OSAT share
• Amkor Technology (US): #2 OSAT; 10-year TSMC Arizona reservation; auto SiC focus
• JCET Group (China): #3 OSAT, #1 in China; full WLP/2.5D/3D/SiP portfolio
• Tongfu Microelectronics (TFME, China): AMD's largest packaging supplier (>80% of AMD orders)
• Powertech Technology (Taiwan): Memory packaging; flip-chip

11.3 The CoWoS Bottleneck & HBM

TSMC CoWoS is the single most constrained resource in AI infrastructure. NVIDIA reserved ~60% of TSMC's 2026 CoWoS capacity. Yields at 2.5D are ~75%. HBM3E stacks come from SK hynix (NVIDIA preferred), Samsung, and Micron. HBM cost per chip: USD 1,200–2,400. CoWoS + HBM can add USD 1,500–3,000+ to a single AI accelerator's BOM.

12. Cost Structure: Where the Money Goes

12.1 NRE Cost Per Design

12.2 Per-Wafer Cost by Node

12.3 Cost Stack as % of Finished Chip (Leading-Edge SoC)

12.4 NVIDIA H100 BOM (Worked Example)

For AI accelerators, packaging + HBM exceed the cost of the logic die — the opposite of conventional chip economics.

13. Geographic Concentration, Monopolies & Choke Points

13.1 Concentration Map by Function

13.2 Concentration by Country / Region

Taiwan

Manufacturing center of gravity: ~63% of foundry revenue (TSMC + UMC + Vanguard + PSMC). Hsinchu Science Park hosts all leading nodes. Geopolitical concentration risk is the single biggest issue facing global tech.

South Korea

Memory powerhouse: Samsung + SK hynix = ~75% DRAM, ~50% NAND, HBM leadership.

Japan

Materials & equipment superpower: ~90% coater/developers, ~53% wafers, ~91% photoresists, large share of specialty gases. Government investing 0.71% of GDP (USD 25.7B) in semiconductors.

United States

Design + EDA + IP + key WFE. HQ of Intel, NVIDIA, AMD, Qualcomm, Broadcom, Apple Silicon, Synopsys, Cadence, Applied Materials, Lam, KLA. CHIPS Act building TSMC Arizona, Intel Ohio/Arizona, Samsung Texas, Micron New York.

Netherlands & Germany

ASML Veldhoven (EUV); Carl Zeiss SMT (optics); Trumpf (CO₂ lasers); Siltronic; Infineon; Bosch; GlobalFoundries Dresden; future TSMC Dresden (ESMC JV). "Silicon Saxony" cluster.

China

World's largest consumer; building domestic supply. SMIC (foundry), CXMT (DRAM), YMTC (NAND), AMEC/Naura (WFE), SMEE (lithography), Empyrean (EDA). Subject to US export controls. Strategy: dominate mature nodes (28nm+), push for sub-14nm self-sufficiency.

14. Application Deep Dives

14.1 Space & Satellite Electronics

Space hardware uses 250nm–90nm (some 65nm/28nm RHBD) for radiation tolerance. Rad-hard suppliers: BAE Systems (Manassas VA), Honeywell (Plymouth MN), Cobham/Caes, Microsemi/Microchip, STMicro, TI HiRel, Frontgrade Technologies. Modern megaconstellations (Starlink, OneWeb) push COTS-with-RHBD to lower cost.

14.2 Defense & Avionics

• Cruise missile guidance: 130nm–65nm (radiation-tolerant)
• Phased-array radar T/R: 150nm SiGe BiCMOS or 65/45nm SOI
• Fighter avionics (legacy): 90nm–65nm; F-35 upgrades: 28nm–14nm
• Ground C4ISR: commercial 16/14/7nm with security overlay
• Cryptographic modules: 130nm–90nm rad-hard SOI

14.3 Automotive

• Powertrain MCUs: 90nm, 65nm, 40nm — Renesas, Infineon, NXP, STMicro
• Radar (24/77/79 GHz): 22nm FDX, 28nm RFCMOS — NXP, Infineon, TI
• ADAS L2+: 16nm, 7nm — Mobileye, NVIDIA, Tesla
• Autonomous L4: 7nm, 5nm, 4nm — NVIDIA Drive Thor, Mobileye EyeQ Ultra
• EV inverters: SiC — Wolfspeed, Infineon, ON Semi, ROHM, STMicro
• EV chargers: GaN — Power Integrations, Navitas, Infineon

14.4 AI / High-Performance Computing

• Training: TSMC 4nm/3nm + CoWoS + HBM3E/HBM4 — NVIDIA H100/B200, AMD MI300X, Google TPU v5/v6
• Inference: 7nm–3nm — Groq, Cerebras, Tenstorrent, Apple Neural Engine
• Server CPUs: TSMC 5nm/3nm (AMD Epyc, AWS Graviton 4, NVIDIA Grace), Intel 18A (Clearwater Forest)
• Switch silicon (51.2T+): TSMC 5nm/3nm — Broadcom Tomahawk 5/6, Marvell Teralynx

14.5 Smartphones & Mobile

• Premium SoC: TSMC N3E — Apple A18 Pro, Snapdragon 8 Elite, Dimensity 9400
• Mid-range: 6nm/7nm · Low-end: 12nm/16nm
• Image sensors: Sony, Samsung, OmniVision — BSI/stacked at 65/45/28nm

14.6 IoT, Wearables, Industrial

• Bluetooth/Wi-Fi/Matter SoCs: 22FDX, 40nm, 55nm — Espressif, Nordic, Silicon Labs
• MCUs: 40nm/55nm/90nm (high volume, lowest cost)
• Industrial Ethernet, motor control: 90nm/65nm

15. Roadmap: 2025–2032

15.1 Near-Term Node Roadmap

15.2 Technology Inflections

• Backside power delivery (BSPDN): Power rails moved to wafer backside. Intel PowerVia first to ship (18A); TSMC A16; Samsung SF1.4.
• High-NA EUV (NA 0.55): ASML EXE:5000 delivers ~8nm half-pitch. First systems shipped to Intel and Samsung 2024–2025.
• Hybrid bonding: Copper-copper diffusion at sub-1µm pitch enables true 3D logic stacking. TSMC SoIC, Intel Foveros Direct.
• CFET: NMOS stacked on PMOS. Imec roadmap ~2031; cost/complexity may stall it.
• 2D channel materials: MoS₂, WSe₂ atomically thin channels. Research only.
• Co-packaged optics: Optical I/O integrated into AI packages. NVIDIA, Broadcom, Marvell 2026–2027.
• Glass substrates: Replace organic substrates for ultra-large packages. Intel + Applied Materials; ~2027 production.

15.3 Strategic Outlook (2025–2030)

• Industry revenue: USD 700.9B in 2025, USD 760.7B in 2026, reaching USD 1 trillion by 2030 (WSTS).
• AI capex driving 35–45% of total semiconductor capex through 2027.
• Geopolitical bifurcation: Western/allied ecosystem for leading edge; China-led at 28nm+ with growing 14/7nm via SMIC.
• End of cost-per-transistor scaling, except via advanced packaging and chiplet disaggregation.
• RISC-V capturing 15–25% of CPU IP starts by 2028 in non-mobile segments.
• EDA becoming AI-native: Synopsys.ai, Cadence Cerebrus, Siemens Aprisa AI.